Full Adder

A full adder is to be implemented using half adders and OR gates. A 4-bit parallel adder without any initial carry requires (AMIE, Electronic Circuits, Summer 2018)

(a) 8 half adders and 4 OR gates
(b) 8 half adders and 3 OR gates
(c) 7 half adders and 3 OR gates
(d) 7 half adders and 4 OR gates


Share this

Related Posts

Previous
Next Post »