Choose the corner answer (2 x 10)
1. The intel 8086 processor is a ____ processor.
(a) 8 bit
(b) 16 bit
(c) 32 bit
(d) 64 bit
2. In 8086 microprocessor the address bus is ____ bit wide.
(a) 10 bit
(b) 12 bit
(c) Mbit
(d) 20 bit
3. An I/O processor controls the flow of information between
(a) Each memory and I/O devices
(b) Main memory and I/O devices
(c) Two VO devices
(d) Cache and main memory
4. The instruction. MOV AX, (BX) is an example of
(a) Direct addressing mode
(b) Register addressing mode
(c) Register relative addressing mode
(d) Register indirect addressing mode
5. If an interrupt request given to an input pin cannot be disabled by any means, then the input pin is called:
(a) Maskable interrupt
(b) Non-Maskable interrupt
(c) Maskable interrupt and Non-Maskable interrupt
(d) None of the mentioned
6. In BSR mode, only port C can be used to
(a) Set individual ports
(b) Reset individual ports
(c) Set and reset individual ports
(d) Programmable I/O ports
7. DEBUG is able to troubleshoot only
(a) .EXE files
(b) OBJ files
(c) EXE file and OBJ file
(d) .EXE file and .LST file
8. The priority level of an interrupt of 8051 for which SI (serial interrupt) interrupt is programmed is:
(a) Level 0
(b) Level 1
(c) Level 0 or Level 1
(d) None
9. Consider the sequence of 8085 instructions given below:
LXI H, 9258
MOV A, M
CMA
MOV M, A
Which one of the following is performed by this sequence?
(a) Contents of location 9258 are moved to the accumulator
(b) Contents of location 9258 are compared with the contents of the accumulator
(c) Contents of location 9258 are complemented and stored in location 9258
(d) Contents of location 5892 are complemented and stored in location 5892
10. Some of the pins of 8085 CPU and their functions are given below. Identify the correct answer that matches the pins to their respective functions.
Group A
P. RST 7.5
Q.HOLD
R. 10/M
S. ALE
Group B
1. Selects IO of memory
2. Demultiplexes the address and data bus
3. Is a vectored interrupt
4. Facilitates direct memory access
5. Is a clock.
6. Selects BCD mode of operation
(a) P-3, Q-2, R-2, S-4
(b) P-4, Q-l, R-5, S-3
(c) P-3, Q-4, R-l, S-2
(d) P-2, Q-3, R-6, S-I
Answers
1. (b) The Intel 8086 was Intel's first x86 processor. Released in 1978, the 8086 began the long line of Intel's most successful architecture, which eventually included the 80286, 80386 and 80486. The 8086 was a 16-bit processor with a 16-bit data bus, 20-bit external bus, 64K I/O ports; it ran at up to 10Mhz.
2. (d) The address bus of an 8086 microprocessor 20 bits wide yet the data bus is 16.
3. (b)
4. (d) This addressing mode allows data to be addressed at any memory location through an offset address held in any of the following registers: BP, BX, DI & SI.
5. (b) A nonmaskable interrupt input pin is one that means that any interrupt request at NMI (nonmaskable interrupt) input cannot be masked or disabled by any means.
6. (c) In BSR (Bit Set-Reset) Mode, port C can be used to set and reset its individual port bits.
7. (a) The DEBUG may be used either to debug a source program or to observe the results of execution of an .EXE file.
8. (b)
9. (a)
This program complements the data of memory location 9258H.
10. (c)
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