Microprocessors and Microcontrollers - MCQs from AMIE exams (Summer 2019)

Multiple Choice Questions ( 2 x 10)

1. In 8085 name/names of the 16-bit registers is/are
(a) Stack pointer
(b) Program counter
(c) Both a and b
(d) None of these

2. Which is used to store critical pieces of data during subroutines and interrupts:
(a) Stack
(b) Queue
(c) Accumulator
(d) Data register

3. Each memory location has
(a) Address
(b) Contents
(c) Both A and B
(d) None of these

4. Basic steps of execution of an instruction is
(a) fetch —> execute —> decode
(b) decode —>  fetch —>  execute
(c) execute —> fetch —> decode
(d) fetch —>  decode —>  execute

5. A microprocessor with a 12-bit address bus will be able to access
(a) 1 KB
(b) 2 KB
(c) 4 KB
(d) 8 KB

6. The instruction of the 8086 microprocessor that is used to transfer the data from the source operand to the destination operand is
(a) data copy/transfer instruction
(b) branch instruction
(c) arithmetic/logical instruction
(d) string instruction

7. BIU strands for
(a) Bus interface unit
(b) Base interface unit
(c) Both a and b
(d) None of these

8. The instruction that is used to complement or invert the bit of a bit addressable SFR of 8051 is 
(a) CLR C
(b) CPL Bit
(c) CPL C
(d) ANL Bit

9. In 8086 microprocessor the following has the highest priority among all type interrupts.
(a) NMI
(b) DIV 0
(c) TYPE 255
(d) OVERFLOW

10. Which processor structure is pipelined?
(a) 8051 processor
(b) 8085 processor
(c) 8086 processor
(d) 8080 processor

Answers

1. (b) 

Different registers of 8085:
  • Accumulator: 8 Bit
  • Program Counter: 16 Bit
  • Stack Pointer: 16 Bit
  • B and C: 8 Bit each
  • D and E: 8 Bit each
  • H and L: 8 Bit each
  • W and Z: 8 Bit each (Temporary Internal Registers)

2. (a) Stacks in Data Structures is a linear type of data structure that follows the LIFO (Last-In-First-Out) principle and allows insertion and deletion operations from one end of the stack data structure, that is top.

3. (c) Each memory location has a physical address which is a code. The CPU can use the code to access the memory location.

4. (d) The process of fetching and executing instructions, one at a time, in the order of increasing addresses is known as straight-line sequencing. n instruction cycle (also known as the fetch–decode–execute cycle or the fetch-execute cycle) is the basic operational process of a computer. It is the process by which a computer retrieves a program instruction from its memory, determines what actions the instruction dictates, and carries out those actions. machine cycle.

5. (c) 2¹² = 4 KB

6. (a) 

7. (a) BIU takes care of all data and addresses transfers on the buses for the EU like sending addresses, fetching instructions from the memory, reading data from the ports and the memory as well as writing data to the ports and the memory. 

8. (b) CPL complements operand, leaving the result in the operand. If the operand is a single bit then the state of the bit will be reversed. If the operand is the Accumulator then all the bits in the Accumulator will be reversed.

9. (a) A non-maskable interrupt (NMI) is a type of hardware interrupt (or signal to the processor) that prioritizes a certain thread or process. Unlike other types of interrupts, the non-maskable interrupt cannot be ignored through the use of interrupt masking techniques. Common examples of non-maskable interrupts include types of internal system chipset errors, memory corruption problems, parity errors and high-level errors needing immediate attention.

10. (c) All x86 processors have pipelined structures.

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