Computer Architecture - MCQs from AMIE exams (Winter 2019)

Multiple Choice Questions (2 x 10)

1. Which determines the address of I/O interface?
(a) Register select
(b) Chip select
(c) Both of above
(d) None of above

2. Whenever the CPU detects an interrupt, what is done with the current state?
(a) Save it
(b) Discard it
(c) Depends on the system to system
(d) First finish it

3. A microprogram is sequencer perform the operation?
(a) Read
(b) Write
(c) Read and Write
(d) Read and Execute

4. Which among following is an important data transfer technique?
(a) CAD
(b) CAM
(c) DMA
(d) MMA

5. RISC stands for?
(a) Risk Instruction Source Computer
(b) Reduced Instruction Set Computer
(c) Risk Instruction Set Computer
(d) Risk Instruction Set Computing

6. The performance of the cache memory is measured in terms of?
(a) Hit Ratio
(b) Chat Ratio
(c) Copy Ratio
(d) Data Ratio

7. A set of physical addresses is also known as?
(a) Disk Space
(b) Address Space
(c) Memory Space
(d) Locations

8. Which interrupt establishes a priority over the various sources to determine which request should be entertained first?
(a) Polling
(b) Daisy chaining
(c) Priority interrupt
(d) All of above

9. Multiprocessor uses large caches but limited process that shares —?
(a) Control bus
(d) Memory bus
(c) Multiple memory bus
(d) Single memory bus

10. In stack organization the insertion operation is known as?
(a) Pop
(b) Push
(c) Down
(d) Upper

Answers

1. (c) 

2. (a) CPU detects an interrupt, what it does with the current state just save it to avoid losing the data without meeting any trouble of it. Additional it works well and keeps the systems away from the common problem without any risk.

3. (c)

4. (c) Direct memory access (DMA) is a method that allows an input/output (I/O) device to send or receive data directly to or from the main memory, bypassing the CPU to speed up memory operations. The process is managed by a chip known as a DMA controller (DMAC).

5. (b) Reduced Instruction Set Computer: A processor architecture that shifts the analytical process of a computational task from the execution or runtime to the preparation or compile time. By using less hardware or logic, the system can operate at higher speeds.

6. (a) The performance of cache memory is frequently measured in terms of a quantity called Hit ratio.
Hit ratio = hit / (hit + miss) = no. of hits/total accesses
We can improve Cache performance using higher cache block size, higher associativity, reduce miss rate, reduce miss penalty, and reduce the time to hit in the cache.

7. (c) In computing, physical address refers to a memory address or the location of a memory cell in the main memory. It is used by both hardware and software for accessing data. Software, however, does not use physical addresses directly; instead, it accesses memory using a virtual address. A hardware component known as the memory management unit (MMU) is responsible for translating a virtual address to a physical address.

8. (c) If multiple devices generate interrupts simultaneously, we have a way to decide which interrupt is to be serviced first. In other words, we have to set a priority among all the devices for systemic interrupt servicing. The concept of defining the priority among devices so as to know which one is to be serviced first in case of simultaneous requests is called a priority interrupt system. This could be done with either software or hardware methods.

9. (d) 

10. (b) Stack is also known as the Last In First Out (LIFO) list. It is the most important feature in the CPU. It saves data such that the element stored last is retrieved first. It can insert an element into or delete an element from the stack. The insertion operation is known as push operation and the deletion operation is known as pop operation.

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