Digital System Design (Short Answer Questions)

Number System

The solution to the quadratic equation k2 − 11k + 22 = 0 are x = 3 and x = 6. What is the base of the number system. (AKTU 2020)

Let, the base = B

Now, the equation is

x2 − 11x + 22 = 0

Now, x = 3

32 − 3(1xB1 + 1xB0) + (2xB1 + 2xB0) = 0

9 − 3(B + 1) + (2B + 2) = 0

B = 8

So, the base is 8.

Hence, we are dealing with Octal.

We will get the same result when we will deal with x = 6.

Find value of x for the following equation: (135)x+(144)x=(323)x (RTU 2019)

If the two numbers are equivalent, they will remain equal in other number systems as well. Converting both the sides to decimal and equating, we get:

(1x2 + 3x1 + 5x0) + (1x2 + 4x1 + 4x0) = 3x2 + 2x1 + 3x0

Hence, x2 + 3x + 5 + x2 + 4x + 4 = 3x2 + 2x + 3

Solving x = 6 (Valid)

These answers are taken from study material for B. Tech. exams for working professionals by amiestudycircle.com. With our study material which is prepared by IIT, Roorkee faculty (Retd.), no text book study is required.

Given that (292)10=(1204)b, determine the value of b. (JNTUH 2023)

29210=1204b=1xb3 + 2xb2 + 0xb1 + 4xb0 = b3 + 2b2 + 4

By trial and error, b = 6.

Write short notes on weighted binary codes. (JNTUH 2023)

In this type of code, each digit/symbol position of the number signifies a specific weight. That is, in weighted code, each decimal digit is expressed by a group of four bits and each bit has a weight of 8, 4, 2, 1.
\(\begin{array}{*{20}{c}}{23}& \to &2&3\\{Code}& \to &{8 + 4 + 2 + 1}&{8 + 4 + 2 + 1}\\{}&{}&{0 + 0 + 1 + 0}&{0 + 0 + 1 + 1}\end{array}\)

Convert binary code (00011011) to gray code. (AKTU 2021)
Answer: 00010110

Find the binary equivalent of 4557. (RGPV 2019, 2020)
Answer: 1000111001101

Find the decimal equivalent of 100110111. (RGPV 2019, 2020)
Answer: 311

Convert (454.523)10 to an hexadecimal number. (AKTU 2023)
Answer: 1C6.85E353F7CE

What is the largest binary number that can be expressed with 14 bits? Determine the equivalent decimal and hexadecimal numbers. (BPUT 2022)

The largest binary number you can represent in 14 bits, assuming no sign bit, is

11 1111 1111 1111, that’s 214 - 1 or 16,383.

111111111111112=3FFF16

= 3FFF16 = 3 x 163 + 15 x 162 + 15 x 161 + 15x160

= 16,3831

111111111111112=16,38310=377778=3FFF16

Convert decimal 8723 to both BCD and ASCII code. For ASCII an even parity bit is to be appended at the left. (BPUT 2022)

Answer: BCD: 1000 0111 0010 0011

ASCII: 1 0111000 0110111 0110010 0110011

Boolean Algebra

State and prove Boolean theorems:

(i) Commutative

(ii) Associative

(iii) Distributive

(JNTUH 2022)

Commutative laws

Commutative law of addition

This law for 2 variables is written algebraically as

A+B = B+A

Cumulative law of multiplication

This law for 2 variables is written algebraically as,

AB = BA

Associative laws

Associative law of addition

This law for 3 variables is written algebraically as,

A+(B+C) = (A+B)+C

Associative law of multiplication

This law for 3 variables is written algebraically as:

A(BC) = (AB)C

Distributive Law

This law is the same as in ordinary algebra. The distributive law for 3 variables is written as follows:

A (B+C) = AB+AC

State and prove consensus theorem. (JNTUH 2023)

How many boolean functions can be made from 3 variables? (RTU 2019)

As the number of variables increases, the number of Boolean functions that can be formed increases rapidly. For three Boolean variables there are 28 = 256 possible Boolean functions, for four variables there are 216 = 65536 possible Boolean functions and for n variables there are possible Boolean functions.

Explain Minterm and Maxterm with example. (AKTU 2023)

Minterm

A minterm of n variables is a product of n literals in which each variable appears exactly once in either true or complimented form, but not both. For example, the list of all the minterms of the two variables x and y are

xy, x’y, xy', x'y'

The list of all of the minterms of three variables

xyz, xyz', xy'z, x'yz, xy'z', x'y'z, x'yz', x'y'z'

Similarly, n variables can be combined to form 2n minterms.

When a Boolean function f is written as a sum of minterms, it is referred to as a minterm expansion or the disjunctive normal form of the Boolean function. It is also called canonical sum of products or standard sum of products.

The following are minterm expansions of Boolean functions

f(x, y) = xy + x'y
f(x, y, z) = x'y'z + x'yz + xy'z' + xyz

Maxterm

A maxterm of n variables is a sum of n literals in which each variable appears exactly once in either true or complicated form, but not both. For example, all maxterm of two variables .r and)’ are

x + y, x' + y, x + y', x' + y'

and all max terms of three variables .v, y and z are

x + y + z, x + y + z', x + y' + z, x' + y + z, x + y' + z', x' + y' + z, x' + y + z', x' + y' + z'

Similarly, n variables forming maxterms, with each variable being complemented or uncomplemented, provide 2n possible combination.

When a Boolean function /is written as a product of maxterm, it is referred to as a maxterm expansion or the conjunctive normal form of the Boolean function. It is also called canonical product of sums and standard product of sums. The following are maxterm expansions of Boolean functions

f(x, y) = (x + y)(x' + y)
f(x, y, z) = (x + y + z)(x + y' + z)(x' + y + z')(x' + y' + z0

Which gates are called universal gates and why? Show that NAND & NOR are universal gates. (AKTU 2021, GTU 2020, 2022, 2023)

NAND and NOR gates are called universal logic gates, because any logic operation can be realized by using these gates.

Consider the NAND gate of figure (a) with input A at both ports.

Draw the circuit diagram of OR gates using discrete components. (JNTUH 2023)

The output will be HIGH, if A or B (or both) are HIGH. Such a logic operation is called OR and is expressed by the Boolean expression

Y = A OR B = A + B

The symbolic representation of OR and its truth table are given in Figs. (a) and (b).

Combinational Circuits

What are Combinational Circuits? (PTU 2020)

Combinational circuit is a circuit in which we combine the different gates in the circuit, for example encoder, decoder, multiplexer and demultiplexer.

The example of Combinational Circuit include:

Half Adder
Full Adder
Half Subtractor
Full Subtractor
Demultiplexer
Encoder
Decoder

Differentiate between combinational logic circuit and sequential circuits? (AKTU 2021, 2022, GTU 2021, 2022, JNTUH 2021, 2022)

Differences Between Combinational and Sequential Logic Circuit

Sequential and combinational logic circuits are the basic building blocks of digital circuits. However, the existence of memory elements makes the main difference. The circuit for combination doesn’t have a memory element, while a sequential circuit is composed of memory elements.
Sequential and combinational logic circuits can generate different outputs. The output from the circuit for combination is a function of the current inputs. However, the output generated by the sequential circuit is dependent on the prior output and current input.
The feedback loop isn’t included in combinational logic circuits. However, any sequential logic circuit should contain it to monitor the output of previous cycles.
The clock signal isn’t utilized in the combinational circuit. However, sequential utilize clock signals to ensure synchronization.
Demultiplexer, decoder, full adder encoder, and half adder are a few examples of combinatorial circuits. Registers and Flip Flops are a few examples of sequential circuits.

What is the role of subtractor in digital electronics? (AKTU 2022)

The subtraction of two binary numbers may be accomplished by taking the complement of the subtrahend and adding it to the minuend. By this method, the subtraction operation becomes an addition operation and instead of having a separate circuit for subtraction, the adder itself can be used to perform subtraction. This results in reduction of hardware.

Write the name of one Parallel Adder. (RTU 2018)

Answer: Ripple carry adder

Q.3. (JNTUH 2018): Interpret 74 x 999 as a full subtractor.

Construct half subtractor using logic gates. (AKTU 2020)

Let us subtract Y from X. The difference bit is D and the borrow bit symbol is B. Here X and Y are inputs and D and B are outputs.

The truth table for half Subtractor is given in the following table.

A half subtractor circuit using NOR gates is given below:

Construct half subtractor using NAND gates. (AKTU 2022)

Half subtractor circuit using NAND gates is given below:

Explain half adder circuit. (GTU 2020)

This circuit adds two binary variables, yields a carry but does not accept carry from another circuit(adder). The truth table of half adder is given in below. (S for sum and C for carry).

From this table

\(\begin{array}{l}S = \bar AB + A\bar B\, = A \oplus B\\C = AB\end{array}\)

S is sum

C is carry

Half adder logic circuit using XOR is shown in given figure.

Half adder circuit using NOR gates is shown in given figure.

Here, \(S = \bar S = \overline {AB + \bar A\bar B} = \overline {(\bar A + \bar B) + (\bar A + \bar B)} \)

Construct a full adder using logic gates. (BPUT 2020, AKTU 2021)

This circuit can add two binary numbers, accept a carry and yield a carry. Such a circuit can easily be visualized by means of two half adders(HA) and an OR as in the given figure.

See following diagram for full adder using NAND gates.

Draw a full adder using two half adders. (AKTU 2023, UTU 2023)

What is the difference between “Ripple Carry Adder” and Carry Look-ahead Generator? (AKTU 2021)

Ripple carry adder

In an RCA, each full adder must wait for the carry-in from the previous full adder before starting its own operation. This can cause a delay, especially when the number of full adders is large.

Carry look-ahead adder

A CLA calculates one or more carry bits before the sum, which reduces the wait time and allows it to add numbers faster than an RCA.

Differentiate between a priority encoder and conventional encoder. (BPUT 2022)

A priority encoder has a priority function which allows it to produce an output corresponding to the highest-order input.

What is the difference between Multiplexer and Encoder. (AKTU 2023)

The digital circuits that perform encoding of digital information are called encoders, while digital circuits that decode the coded digital information are called decoders. An encoder with enable pins is called a multiplexer, while a decoder with enable pins is called a demultiplexer.

Implement a 4:1 multiplexer using 2: 1 multiplexer. (AKTU 2020, 2021)

A logic circuit is given below:

When S1 is set to HIGH it will select i1 and i3 now if s0 is LOW output will have i1 otherwise i3 and similar for i0 and i2.

"PAL has reprogrammable AND array, whereas GAL has programmable AND array". Comment. (PTU 2020)

Reprogrammable AND Array. A PAL features a fixed OR array and a programmable AND array. This means that once the AND connections are programmed, they cannot be changed. However, many modern PALs allow for the reprogramming of the AND array, enabling designers to adjust or modify the logic after the initial programming, which adds flexibility.
GAL (Generic Array Logic). In contrast, a GAL has both programmable AND and OR arrays. Once programmed, the logic can be permanently set. However, GAL devices can be reprogrammed using a specific programming method, allowing for changes in design without needing to replace the physical chip. This feature makes GALs versatile for various applications.

Sequential Circuits

What do you mean by race around condition in JK Flip Flop? (AKTU 2020, 2023, GTU 2023, PTU 2020, UTU 2023)

The solution that we found in the JK flip-flop, for the condition when both the inputs of the flip-flop are high, is not perfect. For the level triggered JK flip-flop of the given figure, consider the case when J = K = 1, Qn = 0 and a clock pulse occurs. After a propagation delay of Dt(<<tp, the pulse width) equal to the delay time of two NAND gates, the output will toggle to Qn = 1. Since this is feedback to the inputs, the output can toggle back to Qn =0 after another delay of Dt, if the clock is still high.

Thus, as long as the clock pulse is present, the output will toggle at every Δ t seconds. This is called race around condition.

Removing race around condition

Making propagation delay Δ t > tp
Passing outputs Qn and through delay lines before feeding them back to input
Use a JK master slave flip-flop

What is flip-flop? Distinguish between Latch and Flip Flop. (AKTU 2020, 2021, JNTUH 2023, RTU 2019, RGPV 2019)

Answer: The most important memory element is the flip-flop, which is made up of an assembly of logic gates. Even though a logic gate by itself has no storage capability, several logic gates can be connected together in ways that permit information to be stored. There are several different gate arrangements that are used to construct flip-flops in a wide variety of ways. A flip-flop (FF), known more formally as a bistable multivibrator, has two stable states. It can remain in either of the states indefinitely. Its state can be changed by applying the proper triggering signal. It is also called a binary or one-bit memory.

A latch is the most basic type of flip-flop circuit. It can be constructed using NAND or NOR gates. Accordingly, the latches are of two types : (i) NAND gate latch and (ii) NOR gate latch

What is the concept of “setup” and “Hold” time? (AKTU 2021)

Answer: Set up time, ts It is the time interval immediately preceding the active edge of the CLK signal during which the control input must be maintained at the proper level.

Hold time, tH It is the time interval immediately following the active edge of the CLK signal during which the synchronous control input must be maintained at the proper level.

State and explain different types of triggering for Flip-flops. (GTU 2021)

Level Triggering

In level triggering, the output changes only when the clock is in HIGH or LOW level. In the clocked SR flip-flop discussed earlier, the output changes according to the input condition as long as clock is HIGH. This is called positive level triggering. If the clock pulse is inverted before applying it to the input, the output will change only when the clock is LOW. This is called negative level triggering.

Edge Triggering

In edge triggering, the output changes only when the clock pulse makes a transition (from LOW to HIGH or from HIGH to LOW). This can be achieved by applying the clock pulse through an RC circuit as shown below.

If this output waveform is applied to the input of a clocked SR flip-flop, the output will change only at LOW to HIGH transition of the clock pulse. This is called positive edge triggering (triggering at the positive edge of the pulse). If the output waveform is inverted and then applied to the input of a clocked SR flip-flop, it will change state only at the HIGH to LOW transition of the pulse, called negative edge triggering. Symbols for all four triggering types are shown below.

What do you understand by state of a machine? Explain briefly. (BPUT 2020, GTU 2021, 2023)

A state machine is a behaviour model. It consists of a finite number of states and is therefore also called finite-state machine (FSM). Based on the current state and a given input, the machine performs state transitions and produces outputs.

Consider the simple state machine above. It consists of two states, Off and On.

On is the initial state here; it is activated when the state machine is executed. The arrows between the states denote the possible state transitions. They define for which input a state change occurs. Here, the active state is changed from On to Off for the input button pressed, and back again to On for the same input.

A state machine is any device storing the status of something at a given time. The status changes based on inputs, providing the resulting output for the implemented changes. A finite state machine has finite internal memory. Input symbols are read in a sequence, producing an output feature in the form of a user interface.

State machines are represented using state diagrams. The output of a state machine is a function of the input and the current state.

Define following terms w.r.t State Machine (GTU 2022, RGPV 2022)

1. State Table

2. State Diagram

State Table

The time sequence of inputs, outputs, and flip-flop states may be enumerated in a state table. The state table for the circuit in Figure (a) is shown in the table in Figure (b).

Clocked sequential circuit

State Table

Here in the table there are three sections designated as present state, next state, and output. The present state designates the states of the flip-flops before the occurrence of the clock pulse. The next state designates the states of the flip-flops after the application of the clock pulse. The output section shows the values of the output variables during the present state. Again, both the output and the next state sections have two columns, one for x = 0 and the other for x = 1.

State Diagram

All the information available in the state table may be represented graphically in the state diagram.

In the diagram, a state is represented by a circle and the transitions between states is indicated by direct arrows connecting the circles. The binary number inside each circle identifies the state the circle represents. The direct arrows are labelled with two binary numbers separated by a /. The number before the / represents the value of the external input, which causes the state transition, and the number after the / represents the value of the output during the present state. For example, the directed arrow from the state 11 to 10 while x = 0 and y = 0, and that on the termination of the next clock pulse, the circuit goes to the next state 10. A directed arrow connecting a circle with itself indicates that no change of the state occurs.

There is no difference between a state table and a state diagram except in the manner of representation. The state table is easier to derive from a given logic diagram and the state diagram directly follows the state table. The state diagram gives a pictorial form of the state transitions and hence is easier to interpret.

Draw the state diagram of any one Finite State Machine (FSM). (RTU 2018)

The state diagram of a finite-state machine that prints the first word of each line of an input stream.

Compare asynchronous and synchronous state machines. (GTU 2022)

Faster
Asynchronous machines are more sensitive to synchronization errors (namely critical race conditions, propagation delay or hazard, oscillation). As a result, it is much more difficult to design reliable asynchronous state machines.
An asynchronous state machine can have stable and transient (or unstable) states.
The operation of an asynchronous state machine can be described using a flow table. A flow table for an asynchronous state machine is identical to a state table for a synchronous machine. It is said to be primitive if each row has only one stable state.
An asynchronous state machine can exit a stable state only if an input changes. It can move from one stable state to another either directly, or transiting through several unstable states or states that do not satisfy the stability condition.
An asynchronous state machine operates in the fundamental mode, provided that only one input changes logic states at a time and then remains constant until a steady state is reached.
For an asynchronous state machine, there is not such a marked difference between Moore and Mealy models as there is with synchronous state machines. In fact, the transitions between states in an asynchronous state machine are always initiated by the inputs, and the outputs are either directly or through state variables, related to the inputs.

Which design style has more number of states--- Mealy or Moore. Why? (BPUT 2020)

Moore model requires more number of states for implementing same function. This often results in a larger number of states because each distinct output requires a separate state.

Explain Moore machine. (GTU 2020, 2023)

The output of the sequential circuit depends only on the present state of the flip-flop, the sequential circuit is referred to as Moore model.

In general form, the Moore model can be represented with its block schematic, as shown in Fig. (a) and (b).

In the Moore model, as output depends only on the present state of flip-flops, it appears only after the clock pulse is applied, i.e. it varies in synchronism with the clock input.

(a) Moore model

(b) Moore circuit model with an output decoder

Explain Mealy machine. (GTU 2020)

The following figure shows the logic diagram of a Mealy model.

Notice that the output depends upon the present state as well as the present inputs. Looking at the figure, we can easily realize that changes in the input during the clock pulse cannot affect the state of the flip-flop. However, they can affect the output of the circuit-Due to this, if the input variations are not synchronized with a clock, the derived output will also not be synchronized with the clock, and we get false outputs. The false outputs can be eliminated by allowing the input to change only at the active transition of the clock.

The behaviour of a clocked sequential circuit can be described algebraically by means of state equations. A state equation (also called transition equation) specifies the next state as a function of the present state and inputs. The Mealy model shown in the figure consists of two D flip-flops, an input x. and an output z. Since the D input of a flip-flop determines the value of the next state.

In general form the Mealy model can be represented with its block schematic as shown in following figure.

What is a finite state machine? (PTU 2020)

The most general model of a sequential circuit has inputs, outputs and internal states. A sequential circuit is referred to as a finite state machine (FSM). A finite state machine is an abstract model that describes the synchronous sequential machine. Since in a sequential circuit the output depends on the present input as well as on the past inputs, i.e. on the past histories and since a machine might have an infinite varieties of possible histories, it would need an infinite capacity for storing them. Since it is impossible to implement machines which have infinite storage capabilities, we consider only finite stale machines.

Finite state machines are sequential circuits whose past histories can affect their future behaviour in only a finite number of ways, i.e. they are machines with a fixed number of states. These machines can distinguish among a finite number of classes of input histories. These classes of input histories are referred to as the internal states of the machine. Every finite state machine therefore contains a finite number of memory devices.

The following figure shows the block diagram of a finite state model. x1, x2, …… xl. are inputs, z1, z2, ……. zm are outputs. y1, y2, ……. yk are state variables, and Y1, Y2, …… Yk represent the next state.

Explain the types of Finite machines. (GTU 2022)

Mealy and Moore. Already explained.

State the advantages and limitations of design procedure using FSM (Finite State Machine) models. (BPUT 2020, JNTUH 2021, 2022, 2023)

Advantages and limitations of FSM

Periodic sequence of finite states: With an n-state machine, we can generate a periodic sequence of n states or smaller than n states. For example, in a n-state machine, we can have a maximum periodic sequence as 0, 1,2,3,4,5,0, 1, .....
No infinite sequence: Consider an infinite sequence such that the output is 1 when and only when the number of inputs received so far is equal to P(P + l)/2 for P= 1,2,3,.... i.e. the desired input-output sequence has the following form:

Such an infinite sequence cannot he produced by a finite state machine.

Limited memory: The finite state machine has a limited memory and clue lo limited memory, it cannot produce certain outputs. Consider a binary multiplier circuit for multiplying two arbitrarily large binary numbers. If we implement this with a finite state machine capable of performing serial multiplication, we can find that it is not possible to multiply certain numbers. Such a limitation does occur due to the limited memory available to the machine. This memory is not sufficient to store arbitrarily large partial products resulted during multiplication.

Define ASM and FSM? (AKTU 2022)

FSM: Already explained.

ASM

The digital system design generally has two distinct parts. One part deals with data processing operations and is represented as data section. The second part deals with control signals generation and supervision and is represented as the control section.

The control section is basically a sequential circuit which generates control signals to control data processing operations by considering the status signals and external signals at any given time. Thus, depending upon the status and external input signals, the sequential circuit goes to the next state to initiate further operations. ASM chart is one of the methods to represent hardware algorithm of control section and data sections.

ASM or simply state machine is another name used for a sequential circuit. These names are used when the sequential circuit is used to control a digital system that carries out a step-by-step procedure or algorithm. A special type of flowchart is called a state machine flowchart or SM chart or ASM chart.

The relation between the data processor and control logic in a digital system is shown below.

Explain different modelling styles in Verilog. (GTU 2020)

Verilog is also an HDL (Hardware Description Languages) for describing electronic circuits and systems. It is used in both hardware simulation and synthesis.

The most popular examples of Verilog are a network switch, a microprocessor, a memory, a simple flip-flop, etc.

A Verilog code can be written in the following styles:

Dataflow style In data flow style of modelling, logic blocks are realized by writing their Boolean expressions.
Behavioural style In the behavioural style of modelling instead of writing Boolean expressions, the behaviour of the logic block is described.
Structural style The structural style is a hierarchical design style in which a logic block is realized in terms of its basic sub-blocks.
Mixed style In mixed style, one can mix up the design styles in their program.

Write a short note/names of different modelling of VHDL. (PTU 2020, RTU 2018, UTU 2023)

Data flow modelling (Design Equations). Data flow modelling can be described based on the Boolean expression. It shows how the data flows from input to output. It works on Concurrent execution.
Behavioural modelling (Explains Behaviour). Behavioural modelling is used to execute statements sequentially. It shows that how the system performs according to the current statement. Behavioural modelling may contain process statements, Sequential statements, Signal assignment statements, and wait statements.
Structural modelling (Connection of submodules). Structural modelling is used to specify the functionality and structure of the circuit. Structural modelling contain signal declarations, component instances, and port maps in component instance.

Write the Verilog code for half adder using gate level modelling. (PTU 2020)

Verilog Code for Half Adder Structural/Gate Level Modelling is given below:

module half_adder(

input i0,

input i1,

output s,

output c

);

and(c,i0,i1);

xor(s,i0,i1);

endmodule

How many flip-flops are needed to implement a 32 bit register? (AKTU 2021)

Answer: A 32-bit register contains 32 flip-flops, each storing a bit.

What is glitch? (BPUT 2022)

Glitch refers to a momentary fault in a system. In digital circuits, a glitch is a short-lived, unexpected voltage spike or signal transition that may occur in a logic circuit due to a race condition. Glitches can cause incorrect behaviour in a circuit and are generally undesirable.

In an asynchronous counter, glitches can occur due to the propagation delay of different logic gates, leading to temporary false outputs during the transition between states. These glitches can be visually represented in a timing diagram by small spikes or irregularities in the waveform at the output signals.

How many flip-flops are required to design a mod 20 counter? (RTU 2019)

For Mod 20 counter, n = 20

Let N be the number of flips flops required, then,

2N ≥ 20 ⇒ N ≥ log2(20)

N ≈ 5 ⇒ N = 5

Compare resisters and counters. (RGPV 2022, VTU 2022)

The register is a storage device that holds a fixed number of bits. It can store and latch data for later use. Registers are commonly used to hold data during arithmetic and logical operations, as temporary storage for intermediate results.

What are the advantages and disadvantages of flash type ADC?(AKTU 2020, 2023)

Advantages

It is the fastest type of ADC because the conversion is performed simultaneously through a set of comparators, hence referred to as flash type ADC. Typical conversion time is 100ns or less.
The construction is simple and easier to design.

Disadvantages:

It is not suitable for higher number of bits.
To convert the analogue input voltage into a digital signal of n-bit output, (2n – 1) comparators are required. The number of comparators required doubles for each added bit.

What is a single slope A/D converter? (PTU 2020)

A single-slope analog-to-digital converter (ADC) is a type of integrating ADC that converts an analog signal into a digital signal. It's the most basic type of integrating ADC and is made up of an integrator, comparator, and digital counter.

List some advantages of successive approximation? (AKTU 2022)

Advantages of Successive Approximation Type A/D Converter

High Accuracy: Successive approximation ADCs offer high accuracy compared to other types of ADCs, making them suitable for applications that require precise measurements.
Speed: They are faster than other types of ADCs, as the conversion process takes only a few clock cycles. This makes them suitable for high-speed applications.
Low power consumption: Successive approximation ADCs consume less power than other types of ADCs, making them ideal for battery-powered devices.
Simple Circuitry: The circuitry of a successive approximation ADC is relatively simple, requiring fewer components than other types of ADCs.
Easy to Interface: They are easy to interface with microcontrollers or digital signal processors (DSPs), making them suitable for use in digital systems.
Noise immunity: Successive approximation ADCs are less susceptible to noise and interference, resulting in a more accurate output.
Flexible Resolution: The resolution of a successive approximation ADC can be easily adjusted by changing the number of clock cycles, making it versatile for different applications.

Where is SAR ADC used? (AKTU 2022)

The development of A/D converters has progressed in a quest to reduce the conversion time. The successive approximation type A/D converter aims at approximating the analogue signal to be digitized by trying only one bit at a time.

The basic step of a 9-bit DAC is 10.3 mV. If 000000000 represents 0 Volts, what is the output for an input of 101101111? (AKTU 2020)

The output voltage for input of 101101111 is

= 10.3 mV (1 x 28 + 0 x 27 + 1 x 26 + 1 x 25 + 0 x 24 + 1 x 23 + 1 x 22 + 1 x 21 + 1 x 20)

= (10.3 x 10-3) x 367 = 3.78 V

Logic Families and Semiconductor Memories

What is logic family? (AKTU 2020, GTU 2023)

Various logic gates such as AND, NOR etc. are nowadays available as Integrated Circuits(ICs). These gates can be designed in any number of ways. Accordingly, there are various logic families, each family of ICs pertains to a particular design. But broadly speaking, there are two main logic families - Bipolar and Unipolar. As the name indicates, the main elements of bipolar logic families are transistors, diodes, and resistors. The main elements of unipolar logic families are MOSFETS.

Characteristics of a Digital IC

The various digital logic families are usually evaluated by comparing the characteristics of the basic gates of each family. The most important governing parameters or properties of various logic families are listed below.

Propagation delay (speed of operation)
Power dissipation
Fan in
Fan out
Noise immunity
Operating temperature
Power supply requirement
Current and voltage parameters

What do you understand by digital TTL? (AKTU 2022)

The TTL or T2L family is so named because of its dependence on transistors alone to perform basic logic operations. It is the most popular logic family. It is also the most widely used bipolar digital IC family. The TTL uses transistors operating in saturated mode. It is the fastest of the saturated logic families. The basic TTL logic circuit is the NAND gate.

State advantages and disadvantages of TTL. (JNTUH 2023)

Advantages of TTL

High speed operation. Fastest among the saturated logic families. The propagation delay time is about 10 ns
Moderate power dissipation
Available in commercial and military versions
Available for wide range of functions
Low cost
Moderate packaging density

Disadvantages of TTL

Higher power dissipation than CMOS
Lower noise immunity than CMOS
Less fan-out than CMOS

Write any one use of tristate logic. (RTU 2028)

One common use of tristate logic is in bus systems within digital circuits. In a bus system, multiple devices can share the same communication pathway. Tristate logic allows a device to either send data onto the bus (driving it high or low) or to enter a high-impedance state (essentially disconnecting from the bus). This prevents conflicts when multiple devices attempt to communicate over the same bus line, ensuring that only one device drives the bus at any given time.

Describe figure of merit & noise immunity of TTL & CMOS ICs. (AKTU 2020, 2023)

Give comparison of TTL and CMOS family. (GTU 2020, 2021, 2022)

Already answered.

Why ECL is the fastest logic family? (AKTU 2022)

ECL is the fastest of the logic families, wherein high speed operation(switch over) results from the fact that the transistors(BJTs) operate between active and cut-off region instead of between saturation and cut-off regions as in other logic families. The operation of an ECL gate is dependent on a differential amplifier, which is the heart of all ECL circuits.

Calculate the fan out of a TTL circuit with the following specifications:

IOL(max) = 32 mA, IIL(max) = 1.6 mA, IOH(max) = 400 mA, IIH(max) = 10 mA.

(BPUT 2022)

Fanout (high) = 400/10 = 40

fanout (low) = 32/1.6 = 20

Hence, Effective fanout = minimum of these two values = 20

Q.1. (RTU 2018, 2 marks): Draw the circuit diagram of any two Dynamic memory cell.

A computer uses RAM chips of 1024 x 1 capacity. How many chips are needed and how should their address lines be connected to provide a memory capacity of 1024 bytes. (BPUT 2022)

RAM chips of capacity 1024 × 1 = 1024 bits

Therefore, for capacity of 16K bytes, i.e. 16 × 1024 × 8 bits.

Hence, Number of chips = 16 x 1024 x 8/1024 = 128 chips

These answers are taken from study material for B. Tech. exams for working professionals by amiestudycircle.com. With our study material which is prepared by IIT, Roorkee faculty (Retd.), no text book study is required.

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